Singaravelan Viswanathan

                                          Singaravelan Viswanathan is a Master’s student in the Electrical and computer Engineering department. He received his Bachelor’s degree in May 2004 from University of Madras, India. He joined the MSVLSI group in January 2006. He is working on creation of a high temperature SOS digital cell library with stacked transistors to improve the leakage performance at extreme temperatures.

                                     The cell library consists of simple and complex logic gates, buffers, multiplexers, flip flops and latches. It is implemented in Peregrine’s 0.5um SOI process and designed to operate at 3.3-5 V power supply for temperatures ranging from 0 to 300 deg C. The development of the cell library involves creating schematics and layout for each cell, characterizing the cells for delay using Signal Storm, generating the abstracted views and the LEF file for automatic layout generation using Place & Route tools.

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